FIG. 11 is a sectional view showing a prior art OEIC. FIG. 12 schematically shows an equivalent circuit of FIG. 11. In the figures, reference numeral 1 designates a GaAs substrate approximately 100 microns thick. A photodiode 2, which converts incident light into electricity, is disposed on the GaAs substrate 1. The photodiode 2 comprises p.sup.+ layers 2c and n.sup.+ layers 2d formed in the surface region of the substrate 1 by ion implantation and p side electrodes 2a and n side electrodes 2b formed the p.sup.+ layers 2c and the n.sup.+ layers 2d, respectively. A field effect transistor (hereinafter referred to as FET) 3 is disposed on the GaAs substrate 1. The FET 3 is a preamplifier for an electronic circuit, which converts the current produced in the photodiode 2 into voltage signals and outputs the voltage signals.
The FET 3 is formed in the following process. First, an active layer 3c and source and drain ohmic contact layers 3d are formed in the surface region of the substrate 1 by ion implantation. Then, a gate metal is deposited on the entire surface of the substrate 1 and selectively etched away to form a gate electrode 3a. Source and drain ohmic electrodes 3b are formed on the source and drain ohmic contact layers 3d at opposite sides of the gate electrode 3a by a spacer lift-off method.
Insulating films 8a for protecting the surface of the substrate 1 are disposed on the substrate 1 where the gate electrode 3a, the ohmic electrodes 3b, and the electrodes 2a and 2b of the photodiode are absent. Inter-layer insulating films 8b are disposed on the insulating films 8a.
In addition, a load resistance 4 of the photodiode 2 is connected to the p side electrode 2a of the photodiode 2. A load resistance 5 is connected to the drain electrode 3b of the FET 3. Reference numeral 6 designates a bonding pad for applying power to the photodiode 2 and the FET 3 or for taking out signals. A wiring 7a connects the p side electrode 2a of the photodiode 2 with the gate electrode 3a of the FET 3 and a wiring 7b connects the electrode 5a of the load resistance 5 with the drain electrode 3b of the FET 3. A protective film 9 is disposed on the entire surface of the wafer. A gold plating layer 10 is disposed on the rear surface of the substrate 1. When the IC chip is mounted on a package, the gold plating layer 10 is adhered to the package by solder or the like. Reference numeral 11 designates an optical fiber as a transmission medium and reference numeral 12 designates light from the optical fiber 11. FIGS. 10(a) and 10(b) are a top view and a bottom view of the OEIC shown in FIG. 11.
A description is given of the operation. When light 12 (an optical signal) having a wavelength of 0.85 micron strikes the photodiode 2 through the optical fiber 11, free holes and electrons are generated in the p.sup.+ layer 2c, the n.sup.+ layer 2d, and a depletion layer between the layers 2c and 2d The electrons in the p.sup.+ layer 2c and the holes in the n.sup.+ layer 2d flow into the depletion layer. The holes and electrons in the depletion layer drift toward the p.sup.+ layer 2c and the n.sup.+ layer 2d, respectively, and a photocurrent is generated in proportion to the intensity of the light. The photocurrent is taken out from the p side electrode 2a. The p side electrode 2a is connected to the gate electrode 3a of the FET 3 and the load resistance 4 of the photodiode 2 by the wiring 7a. When the current taken out from the p side electrode 2a flows into the load resistance 4, the current is converted to a voltage signal and input to the gate electrode 3a of the FET 3. Then, the voltage signal is amplified by the voltage amplifier comprising the FET 3 and the load resistance 5 and taken out from the bonding pad 6 serving as an output terminal.
In the above-described OEIC, the speed of response depends on a CR time constant which is the product of the sum of the capacitance of the photodiode and the input capacitance of the FET (capacitance C) and the load resistance of the photodiode (resistance R). With an increase in the quantity of information transmitted in optical communication, in order to realize a high speed and low noise OEIC, it is necessary to reduce the capacitance of the photodiode 2. A photodiode several tens of microns in diameter is effective to reduce the capacitance component of the photodiode. However, the diameter of the core of the optical fiber 11 through which light 12 is propagated is 10 to 50 microns and the light spreads wider than the diameter of the fiber because of diffraction at the end of the fiber. Therefore, if the precision of alignment between the fiber 11 and the photodiode 2 is poor, the light unfavorably strikes elements other than the photodiode 2. When the light strikes the active layer of the FET, carriers in the active layer are excited due to light-to-electricity conversion and the drain current of the FET unfavorably increases, resulting in a malfunction of the FET.
Meanwhile, FIG. 13 is a cross-sectional view of an OEIC described in Japanese Published Patent Application No. 61-135155. In FIG. 13, a PIN type diode 134 and an FET 135 are integrated on a semi-insulating GaAs substrate 121. More specifically, an n.sup.+ type GaAs layer 122, an n.sup.- type GaAs layer 123, and a high resistance AlGaAs layer 124 are successively disposed on the semi-insulating GaAs substrate 121 and a groove 133 separates the PIN type diode 134 from the FET 135. In the FET 135, an undoped GaAs layer 125 is disposed on the AlGaAs layer 124 and an n type GaAs layer 126 is disposed on the undoped GaAs layer 125. Source, drain, and gate electrodes are disposed on the n type GaAs layer 126. In the PIN type diode 134, a groove 136 is formed in the high resistance AlGaAs layer 124 and a p type region 128 is formed by diffusing zinc from the surface of the groove 136 to reach the n.sup.- type GaAs layer 123. P side electrodes 130 are disposed on the upper end surface of the p type layer 128 and connected to the gate electrode of the FET 135 by an aluminum wiring 131. An n side electrode 132 of the PIN diode 134 is disposed on the n.sup.+ type GaAs layer 122. Silicon nitride films 127 are disposed on the high resistance AlGaAs layer 124 where the p side electrodes 130 and the undoped GaAs layer 125 are absent.
Also in the structure of FIG. 13, light unfavorably strikes the FET 125. In order to prevent the light from being incident on the FET 125, the Japanese Published Patent Application No. 61-135155 proposes a structure shown in FIG. 14, in which an FET 113 and a PIN diode 114 are integrated on a semi-insulating GaAs substrate 105. In FIG. 14, a high resistance AlGaAs layer 104, an n.sup.- type GaAs layer 103, an n type GaAs layer 102, and an n.sup.+ type GaAs layer 101 are successively disposed on the semi-insulating GaAs substrate 105. A gate electrode of the FET 113 is disposed on the n type GaAs layer 102 and source and drain electrodes are disposed on the n.sup.+ type GaAs layer 101 at opposite sides of the gate electrode. The FET 113 is separated from the PIN diode 114 by insulating regions 108. A groove 106 penetrates the substrate 105 to expose the high resistance AlGaAs layer 104 and a p type region 107 is formed by diffusing zinc from the surface of the groove 106. P side electrodes 110 of the PIN diode 114 are disposed on the upper end surface of the p type layer 107 and an n side electrode 109 is disposed on the n.sup.+ type GaAs layer 101. The n side electrode 109 is connected to the gate electrode of the FET 113 by an aluminum wiring 112.
In operation, an optical fiber is inserted in the groove 106 of the diode 114 to generate free electrons in the p type layer 107. The free electrons thus generated travel through the n.sup.- GaAs layer 103, the n type GaAs layer 102, and the n.sup.+ type GaAs layer 101, so that carriers are transferred in a longitudinal direction and taken out from the n type electrode 109. Therefore, in order to provide a path for the carriers, it is necessary to separate the FET 113 from the PIN diode 114 by the insulating region 108, and a restriction is placed on the positional relation between the PIN diode 114 and the FET 113, that is, the degree of freedom in arranging these elements is decreased. As a result, high density integration is not achieved. In addition, since a laminated structure is employed, the production process is complicated, resulting in high costs.